A typical flash ADC uses 2.sup.n -1 comparators to generate n-bit digital values which represent an analog input signal sampled at instants determined by its clock signal. For example, a typical 8-bit ADC uses 2.sup.8 -1=255 comparators. A 10-bit ADC would use 2.sup.10 -1=1023 comparators. Each of these comparators is supplied with an analog input signal and one of 2.sup.n -1 evenly spaced reference values. Comparators having reference values which are less than the input signal value provide a first logic state, for example logic-high, to a decoder while comparators having reference values which are greater than the input signal provide a second logic state, for example logic-low. The decoder is a thermometer type or a priority encoder which translates the 2.sup.n -1 logic values provided by the respective comparators into an n-bit digital value.
Thus, in a flash ADC, the input signal is coupled to each of the 2.sup.n -1 comparators. Each of which presents a load impedance to the input signal. Even if the comparators are designed to have a relatively low input impedance, the sum of the input impedances of all of the comparators can create a significant load which must be driven by the input signal. The relatively large input impedance of comparator arrays having more than 255 comparators makes classic flash-type ADCs impractical for digital values having more than 8 bits. This is true whether the input impedance is resistive and capacitive, such as is found in bipolar circuitry, or primarily capacitive such as is found in metal-oxide-semiconductor (MOS) circuitry.
In addition, relatively large flash ADCs are subject to integral and differential linearity errors. Integral linearity errors usually occur during high-speed operation when the current drawn by the input comparators through the reference ladder network produces significant additional potential drops across the reference resistors. When the reference input ports of the comparators present significant capacitive loads, the amount of current drawn, and thus, the potential drops across the ladder network are proportional to the clock frequency. Differential linearity error is a measure of the error offset of the worst comparator in the array. This type of error may be caused by mismatched or faulty components in an individual comparator or by an individual reference potential which is either too large or too small and generally increases as the number of comparators increases and/or as the potential difference between successive reference levels decreases.
K. Kattmann et al., in "A Technique for Reducing Differential Non-Linearity Errors in Flash A/D Converters," 1991 IEEE International Solid State Circuits Conference, pages 170-171, describe a high-speed ADC which exhibits significantly reduced differential linearity errors. The ADC uses differential preamplifiers to generate output signals each representing a difference between the input signal and a reference value. The output terminals of the preamplifiers are coupled to adjacent preamplifiers by a network of resistors. The resistor network sums the outputs of the preamplifiers surrounding the one which is closest to balance to find an average balance point. If the output signal of the preamplifier nearest to balance is not consistent with this averaged balance point, the resistor network changes the current flow to that preamplifier to adjust its gain and, so, the value of its output signal. This configuration has been found to reduce differential non-linearity errors by adjusting the gains of erroneous differential amplifiers in a sense which tends to reduce the magnitude of their errors.
U.S. Pat. No. 4,928,103 entitled PARALLEL ANALOG-TO-DIGITAL CONVERTER USING 2.sup.(n-1) COMPARATORS describes an ADC which produces n-bit digital values using 2.sup.n /2 input comparators. Each of the input comparators has two complementary output signals. These signals are coupled to respective input ports of a latch which is configured to change state when the output signals of the preamplifier are equal. Signal values between any two reference values are decoded using latches which are coupled to respectively different output terminals of the preamplifiers associated with the two reference levels surrounding the level to be decoded. While this ADC design significantly reduces the loading of the input signal by requiring only 2.sup.n -1 comparators to generate n-bit digital values, no further reduction can be achieved by inserting additional latches between the adjacent preamplifier stages.